1. Field of the Invention
The present invention relates to a data transfer apparatus and a data transfer method. It relates in particular to a data transfer apparatus and a data transfer method, for efficient data transfer from a local bus to a storage unit on a system bus and from the system bus to a storage unit on the local bus.
2. Description of Related Art
Conventionally, data have been transferred via a bus bridge between a system bus to which a CPU is connected and a local bus to which an I/O device is connected. When accessing data in a main memory of the system bus from the I/O device, a request is first made to the bus bridge, then the bus bridge acquires a use authority of the system bus, so as to generate a read cycle on the system bus to the main memory. After the data are obtained, the data are transferred to the local bus.
Next, a conventional data transfer apparatus will be described in detail, with reference to accompanying drawings.
FIG. 7 illustrates a schematic configuration showing a concept of the conventional data transfer apparatus. In FIG. 7, numeral 1 denotes a CPU, numeral 2 denotes a bus arbitration unit, numeral 3 denotes a main memory, numeral 4 denotes an I/O device, numeral 5 denotes a bus bridge, numeral 6 denotes a bridge control unit, numeral 7 denotes a bus arbitration unit, and numeral 8 denotes an address/data control unit. The CPU 1, the bus arbitration unit 2 and the main memory 3 are provided on a system bus, while the I/O device 4 is provided on a local bus.
FIG. 8 shows a timing chart in the case where the I/O device 4 on the local bus causes data to be transferred from the main memory 3 via the bus bridge in the conventional data transfer apparatus described above. As one example, the case of transferring data from address “4000” in the main memory 3 is shown in this figure.
In FIG. 8, numerals 51 to 56 indicate the status of the system bus. Numeral 51 indicates the status of a use authority of the system bus, numeral 52 indicates that of a request signal line from the bus bridge 5 to the bus arbitration unit 2, numeral 53 indicates that of an acknowledge signal line from the bus arbitration unit 2 to the bus bridge 5, numeral 54 indicates that of an address line on the system bus, numeral 55 indicates that of a data line on the system bus, and numeral 56 indicates that of a read/write line on the system bus. Numerals 57 to 61 indicate the status of the local bus. Numeral 57 indicates the status of a request signal line from the I/O device 4 to the bus arbitration unit 7, numeral 58 indicates that of an acknowledge signal line from the bus arbitration unit 7 to the I/O device 4, numeral 59 indicates that of an address line on the local bus, numeral 60 indicates that of a data line on the local bus, and numeral 61 indicates that of a read/write line on the local bus.
The timing chart of FIG. 8 describes the processing by assuming the following operation. Before a data transfer request is generated from the I/O device 4, on the system bus, the CPU 1 writes data to addresses “4000”, “4004” and “4008” in the main memory 3 as indicated by numerals 71 to 78.
The following is a description of an operation in the case where a request to read data at the address “4000” in the main memory 3 is generated from the I/O device 4 during the above write operation to the main memory 3 on the system bus.
First, as indicated by numeral 79, the request signal line is asserted so as to request a bus use authority from the bus arbitration unit 7. Next, as indicated by numeral 80, the acknowledge signal line is asserted by the bus arbitration unit 7. Then, as indicated by numeral 81, the bus arbitration unit 7 asserts the request signal line so as to request the use authority of the system bus from the bus arbitration unit 2. Also, as indicated by numeral 82, the address “4000” is driven on the local bus by the I/O device 4.
The bus arbitration unit 2 adjusts a timing of assigning the use authority of the system bus. The bus arbitration unit 2 does not assert the acknowledge signal line to the bus arbitration unit 7 until the data transfer executed on the system bus ends. After the CPU 1 finishes the data transfer, the bus arbitration unit 2 asserts the acknowledge signal line as indicated by numeral 83, so as to permit the bus bridge 5 to use the bus. Subsequently, as indicated by numeral 84, the address “4000” is driven on the system bus from the address/data control unit 8, so that the data is transmitted from the main memory 3 as indicated by numeral 85. Then, as indicated by numeral 86, this data is driven on the local bus to be received by the I/O device 4, thus completing the data transfer.
However, the conventional data transfer apparatus described above has the following problem. When the system bus is in use, the bus arbitration units 2 and 7 cooperate to carry out the bus arbitration. Thus, a time delay is generated in the process where the bus bridge 5 acquires the use authority of the system bus so as to access the main memory 3 on the system bus, thus transferring the data from the main memory 3 to the bus bridge 5. As a result, the data transfer becomes slow.